| ?/TD> |
| Microsoft DirectX 9.0 |
The pixel shader processor has two parallel pipelines: one for vector processing (RGB) and one for scalar processing (alpha). As a result, pixel shaders allow potentially different arithmetic operations to be performed concurrently in the RGB and alpha pipes.
A destination Register Write Masks can affect how the two pipelines are allocated, but there can be ambiguities in the order of operations unless explicit pairing syntax is used. The following table illustrates the destination register write masks and their associated pipe.
| Destination register write mask | Pipe |
|---|---|
| .a | The operation is in the scalar pipe. |
| .rgb | The operation is in the vector pipe. |
| .rgba | The operation is in both the scalar and vector pipes. It already counts as a pair. |
Pairing, or co-issuing, is indicated by a plus sign (+) preceding the second instruction of the pair.
mul r0.rgb, t0, v0 // Component-wise multiply of the colors. + add r1.a, r1, c2 // Add an alpha component at the same time.
The dot product instructions are a special case. They are vector operations and are always run in the vector pipeline. However, you still have the option to specify a different instruction in the scalar pipe and still get pairing.
dp3 r0.rgb, t0, v0 + mul r0.a, r1, c2
The destination register for co-issued instruction pairs can be different.