|Microsoft DirectX 9.0|
Write masks control which channels (red, green, blue, alpha) are updated in the destination register.
Destination register. For more about register types, see Registers - ps_1_X.
The following destination write masks are available.
|1.0||1.1||1.2||1.3||1.4, 2.0, 3.0|
|red, green, blue, alpha||destination register.rgba||X||X||X||X||X|
|color (red, green, blue)||destination register.rgb||X||X||X||X||X|
|arbitrary||destination register.rgba||See following note.|
If no destination write mask is specified, the destination write mask defaults to the rgba case. In other words, all channels in the destination register are updated.
An alternate syntax for the r,g,b,a channels is x,y,z,w.
For versions 1.0 to 1.3, the dp3 arithmetic instruction can use only the .rgb or .rgba output write masks.
Destination register write masks are supported for arithmetic operations only. They cannot be used on texture addressing instructions, with the exception of the version 1.4 instructions, texcrd and texld.
The default is to write all four color channels.
// All four color channels can be written by explicitly listing them. mul r0.rgba, t0, v0 // Or, the default mask can be used to write all four channels. mul r0, t0, v0
The alpha write mask is also referred to as the scalar write mask, because it uses the scalar pipeline.
add r0.a, t1, v1
So this instruction effectively puts the sum of the alpha component of t1 and the alpha component of v1 into r0.a.
The color write mask is used to control writing to the color channels.
// The color write mask is also referred to as the vector write mask, // because it uses the vector pipeline. mul r0.rgb, t0, v0
For version 1.4, destination write masks can be used in any combination as long as the masks are ordered r,g,b,a.
// This example updates the red, blue, and alpha channels. mov r0.rba, r1
A co-issued instruction allows two potentially different instructions to be issued simultaneously. This is accomplished by executing the instructions in the alpha pipeline and the RGB pipeline.
// For example, the default example shown above: mul r0, t0, v0 // is also equivalent to the following co-issued instruction mul r0.rgb, t0, v0 + mul r0.a, t0, v0
The advantage of pairing instructions this way is that it allows different operations to be performed in the vector and scalar pipeline in parallel.