Integration of Pixel Shaders into the Graphics Pipeline

Pixel processing is performed by pixel shaders on individual pixels. Pixel shaders can work by themselves or in concert with vertex shaders and streams. You cannot program pixel shaders in a vacuum; they depend on the upstream components.

The sequence of operations in the pixel pipeline is as follows:

• Triangle setup
• Pixel shader (replaces fixed format multitexture)
• Iterate colors, texcoords, etc.
• Sample textures
• Texture/color blend
• Fog blend
• Alpha, stencil, depth testing
• Frame-buffer blend

The inputs to the pixel shader come from the outputs of the vertex shader. Registers v0 and v1 contain the vertex colors from vertex shader output registers oD0 and oD1. The textures in the color stages, referenced by pixel shader instructions like tex t0, are sampled using the texture coordinates in the vertex shader output register corresponding to that stage, like oT0. Pixel shaders use color and alpha-blending instructions and texture-addressing instructions to manipulate these inputs and calculate a result. The result emitted by the pixel shader is the contents of register r0 or the output pixel color. Whatever it contains when the shader completes processing is sent to the fog stage and render target blender for further processing. Vertex shader outputs can provide pixel shader inputs.

The ps_3_0 shader model has a few different concepts from ps_1_X/ps_2_0.

• In version 3_0 pixel shaders, the final fog blending is expected to be performed by the pixel shader. Consequently, the fog blending stage of the pixel pipeline is disabled and pixel shader output is sent to the alpha/stencil/depth testing stage of the pixel pipeline.
• Version 3_0 vertex shaders no longer support color (oDn) or texture (oTn) registers. They now use output (on) registers whose meaning is defined by declaration instructions in the vertex shader. For more information about registers or declarations in vs_3_0, see Registers - vs_3_0. See dcl_usage.