Registers - vs_3_0

One additional register is introduced in this version. This section contains reference information for the input and output registers implemented by vertex shader version 3_0.

Input Registers

Name	Register type	Count	Data type	Dimension	I/O permissions	Read port	Read / Instruction	Rel-Address	Defaults	Requires DCL
v#	Input Register	16	floating-point	4-D vector	read	1	3	no	Partial(0001)	yes
r#	Temporary Register	12 (1)	floating-point	4-D vector	read / write	3	3	no	none	no
c#	Constant Float Register	256 (2)	floating-point	4-D vector	define / read	1	2	a0 / aL	(0, 0, 0, 0)	no
i#	Constant Integer Register	16	integer	4-D vector	define / use	1	1	no	(0, 0, 0, 0)	no
b#	Constant Boolean Register	16	boolean	scalar	define / use	1	1	no	FALSE	no
a0	Address Register	1	integer	4-D vector	write / use	1	2	no	none	no
aL	Loop Counter Register	1	integer	scalar	use	1	2	no	none	no
p0	Predicate	1	boolean	4-D vector	write / use	1	1	no	none	no
s#	Sampler Register	4	R	1	1	1	No	None	Yes	Yes

Where:

r is read, w is write, u is used.
partial(x, y, z, w) - If only a subset of channels are updated in the register, the remaining channels will default to specified values (x, y, z, w).
The number of readports is the number of different registers (for each register type) that can be read in a single instruction. For example, a readport of two for a constant register means that all of these are legal since they use 2 or fewer unique constant registers:
```
mad r0, c0, c0, c1 
mad r0, c2, t1, c1 
mad r0, c3, c3, c3 
```
But the following is illegal because it uses mnore than 2 unique constant registers:
```
mad r0, c1, c2, c3
```

(1) - 12 is the minimum r# register counted required by vs_2_x. The D3DCAPS9.VS20Caps.NumTemps cap contains the actual r# register count supported by the device. See D3DCAPS9.

(2) - 256 is the minimum c# register count required by vs_2_x. The MaxVertexShaderConst cap contains the actual c# register count supported by the device. See D3DCAPS9.

Register Defaults

It is unwise to use uninitialized address or temporary registers. All other defaults are specified in the table above.

Output Registers

Output registers have been collapsed into 12 o# (output) registers. These can be used for anything the user wants to interpolate for the pixel shader: texture coordinates, colors, fog, etc.

Register type	Count	R/W	# Read ports	# Reads/inst	Dimension	RelAddr	Defaults	Requires DCL	New
Output Register - on	12	W	N/A	N/A	4	aL only	None	Yes	Yes

Output declarations are introduced, whereby semantics are assigned to each register. Old oPos and oPts are replaced by declaring an o register with a position or pointsize semantic, further described below.

All four components of one of the 12 output registers must be declared as a position register (for example: dcl_position0 v#).
Ten other registers are also 4-component registers (xyzw). The remaining register can contain scalar pointsize data (for example: dcl_psize o#).

See dcl_usage for examples declaring output registers.

Indexing Registers Extended

In the earlier shader models, only the constant register bank could be indexed. In this model, the following register banks can be indexed using the loop counter register (aL).

Input registers (vn)
Output registers (on)